1. Field of the Invention
The present invention relates to a data processing system having a buffer management function using a BDL (Buffer Descriptor List).
2. Description of the Related Art
One block of data of an external storage device can be written in different areas of a main memory, and can be read out from the different areas of the main memory using data chaining. This method is called a scatter read or gather write method. When data transfer is performed between a divided physical storage space and an I/O device, like in the scatter read or gather write method, the I/O device accesses memory by treating buffers scattered on the physical storage space as one continuous I/O buffer. A kind of list or table called a BDL (Buffer Descriptor List) is prepared to achieve such access.
A method of accessing memory using the BDL will be described below with reference to FIGS. 1 and 2. In FIG. 1, one block of data is divided into (n+1) subblocks which are stored in areas 0 to n of a physical storage space. The BDL is constituted as a list of (n+1) BDWs (Buffer Descriptor Words). Each BDWi (BDW0, BDW1, . . . ) corresponds to an ith storage area in the physical storage space. The BDWi consists of an address portion Ai (A0, A1, . . . ) indicating a start address of the ith storage area, and a length portion Li (L0, L1, . . . ) indicating a length (number of bytes) of the storage area.
FIG. 2 shows a conventional operation flow diagram of a CPU when DMA (Direct Memory Access) is performed using the BDL. When a CPU receives from a DMAC (Direct Memory Access Controller) a transfer end interruption signal indicating that transfer of data to a given storage area is completed, it checks if memory access is completed (step S1). If YES in step S1, control returns to a main routine. If NO in step S1, the CPU updates a pointer indicating a number of a BDW to be executed (i.e., a number of a buffer to be accessed) (step S2). The CPU sets the BDWi indicated by the pointer in the DMAC (step S3). The CPU sends a start instruction to the DMAC (step S4). Thereafter, control returns to the main routine.
In response to the start instruction from the CPU, the DMAC sequentially transfers data from the location of the start address Ai. When a total volume of transferred data coincides with a data volume represented by the length portion Li, the DMAC outputs a transfer end interruption signal to the CPU, and ends processing of the storage area. Upon reception of the transfer end interruption signal, the CPU repeats the processing shown in FIG. 2.
In the above processing, the CPU must program the DMAC in units of BDWs. More specifically, every time DMA for a given storage area is completed, the CPU must intervene in the operation of the DMAC. When an object to be accessed is a disk, this intervention time causes a rotational wait time of the disk, thus degrading system performance. When the object to be accessed is a magnetic tape, this intervention time may cause a timing error. When the object to be accessed is a line system, over-run/under-run may occur. Since overhead time is caused, operation of the entire system is delayed.